FIG. 1 shows a conventional BiNMOS inverter. It comprises a first NPN transistor 29 in which the collector is connected to a high potential power source (hereinafter referred to as Vcc) 1 and the emitter is connected to an output terminal 8, NMOS 30 in which the source, drain and gate are connected to GND 2, output terminal 8 and input terminal 7, respectively, PMOS 31 in which the source, drain and gate are connected to Vcc 1, the base of the NPN transistor 29 and input terminal 7, respectively, and NMOS 32 in which the source, drain and gate are connected to GND 2, the base of the NPN transistor 29 and input terminal 7, respectively.
Herein, the gate width of NMOS 30 is set at that required to pull down a given load capacitance at a sufficient speed. For example, the gate width is 10 .mu.m. The gate width of PMOS 31 is set to sufficiently shorten the time to charge the base of the NPN transistor 29. For example, the gate width is 12 .mu.m. The gate width of NMOS 32 is set to sufficiently fast pull down the parasitic capacitance around the base of the NPN transistor 29. For example, the gate width is 5 .mu.m.
In operation, when the potential of the input terminal 7 is changed high to low, PMOS 31 turns on and NMOS 32 simultaneously turns off thereby turning on the NPN transistor 29 to charge a load capacitance. Here, NMOS 30 turns off thereby not flowing a penetrating current between the NPN transistor 29 and NMOS 30.
When the potential of the input terminal 7 is changed low to high, PMOS 31 turns off and NMOS 32 simultaneously turns on thereby cutting off the base current for the NPN transistor 29 to reduce the base potential. Here, NMOS 30 turns on, thereby discharging the load capacitance to get down the output potential. If the gate width of NMOS 32 is set such that the falling speed of the base potential of the NPN transistor 29 is faster than that of the potential of the output terminal, the NPN transistor 29 continues to turn off to stop the penetrating current.
The power consumed in the above operation is mainly a power for the charge-and-discharge of the gate capacitance of MOS transistor and source and drain diffusion capacitance.
FIG.2 shows a conventional CMOS inverter. PMOS 9 is used for pulling up the output potential and NMOS 10 is used for pulling down the output potential.
It is known that the gate width ratio of PMOS 9 and NMOS 10 is set about 2:1 to obtain the highest speed, since ON current per unit gate width of PMOS is about 1/2 that of NMOS. Furthermore, the rise and fall time of the output potential can be balanced. For example, the gate widths of PMOS 9 and NMOS 10 are set to 20 and 10 .mu.m, respectively.
As the gate width of PMOS 9 is reduced, the rise time of the output becomes longer. However, since the logical threshold is simultaneously reduced, the operating speed in the case of connecting a gate with the same circuit constant is not highly degraded. Thus, in a gate array etc., to give priority to the integration density and consumed power, the gate width ratio of PMOS and NMOS 10 may be reduced to about 1.2:1. In this case, the gate widths of PMOS 9 and NMOS 10 are, for example, set 12 and 10 .mu.m, respectively.
However, it is not preferable that the ratio is less than 1.1. Because, in the case that a constant total gate width is set, if a larger gate width is assigned to NMOS therefrom, the consumed power is not reduced and the operating speed is decreased.
The operation speeds of the above-mentioned CMOS gate circuit and BiNMOS gate circuit are generally equal under a low load condition. Therefore, when a circuit block with a complex logic is composed, the main section is generally composed of the CMOS gate circuit which facilitates to compose the circuit and has a high integration density and BiNMOS is used only for the output section and a section with a large fan-out.
The above logical circuits can be composed as a master-slice type semiconductor integrated circuit in which arrays of transistors, resistance elements, etc., are previously placed on a semiconductor substrate and the elements on the substrate are interconnected on the wiring process.
FIG. 3 shows a basic cell layout for a conventional BiNMOS gate array. Two PMOSs 34 and 35 are formed on a common diffusion region 33 and have commonly a diffusion region contact.
Similarly, two NMOSs 37 and 38 are formed on a common diffusion region 36 and have commonly a diffusion region contact. Also, two small NMOSs 40 and 41 are formed on a diffusion region 39 separated from NMOSs 37 and 38, and a NPN transistor 42 is provided.
The gate widths of PMOSs 34, 35, NMOSs 37, 38 and small NMOSs 40, 41 are set to 12 .mu.m, 10 .mu.m and 5 .mu.m, respectively.
For example, in the BiNMOS inverter in FIG. 1, NPN 42 is used as the NPN transistor 29, PMOS 34 or 35 is used as PMOS 31, NMOS 37 or 38 is used as NMOS 30 for output pull-down, and NMOS 40 or 41 is used as NMOS 32.
In a further complex logical block, a BiNMOS gate is used in an output drive section and a CMOS gate is used in a logical composition section. Thus, NMOS 30 for output pull-down of the BiNMOS gate and NMOS used in the logical composition section have the same gate width since they use NMOSs 37 and 38 in FIG. 3.
Also, PMOS 31 for driving the base of the NPN transistor 29 of the BiNMOS gate and PMOS used in the logical composition section have the same gate width since they use PMOSs 34 and 35.
FIG. 4 shows a basic cell layout for a conventional CMOS gate array. Two PMOSs 44 and 45 are formed on a common diffusion region 43 and have commonly a diffusion region contact. Similarly, two NMOSs 47 and 48 are formed on a common diffusion region 46 and have commonly a diffusion region contact. The gate widths of PMOSs 44, 45 and NMOSs 47, 48 are set to 12 .mu.m and 10 .mu.m, respectively.
FIG. 5 shows another example of a basic cell layout for a conventional BiNMOS gate array which is disclosed in U.S. Pat. No. 5,055,716.
In the above example, transistors used only for each of a CMOS logical section 49 and a BiNMOS buffer section 50 are provided in the basic cell. Though the CMOS logical section 49 can use MOS transistors with gate widths smaller than that of MOS transistors used in the BiNMOS buffer section 50, the place where the BiNMOS buffer is composed must be limited since a NPN transistor does not exist in the CMOS logical section.
Thus, when small logical blocks such as a BiNMOS inverter are continuously disposed, or when a gate which has few numbers of output regardless of many MOS transistors, for example, a 16:1 selector, is placed, useless transistors will be left since the BiNMOS buffer section is not used so frequently.
As described above, in the conventional BiNMOS logical integrated circuit, even when the gate width of NMOS for output pull-down in a BiNMOS gate and the gate width of NMOS in a CMOS gate are equal, or the gate width of NMOS in the CMOS gate is shortened by changing the size, the former leads to an increase in consumed power and a decrease in integration density and the latter leads to a lack of integration density. As a result, it can not realize a high integration density and low consumed power as compared with the same generation CMOS logical integrated circuit.